cv
Basics
| Name | Egor Namakonov |
| e.namakonov@cs.au.dk | |
| Url | https://fresheed.github.io |
| About | PhD student working on formal verification of concurrent programs |
Education
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Sep 2022 - Present Aarhus, Denmark
PhD, Aarhus UniversityComputer Science
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Sep 2018 - Jul 2020 St. Petersburg, Russia
Master, St Petersburg UniversityComputer Science
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Sep 2013 - Jul 2017 St. Petersburg, Russia
Bachelor, Peter the Great St. Petersburg Polytechnic UniversitySoftware Engineering
Industrial experience
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Jul 2019 - Aug 2022 St. Petersburg, Russia
Intern and junior researcher, JetBrains ResearchWeak memory research, teaching
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Nov 2015 - Jul 2018 St. Petersburg, Russia
Intern and DevOps engineer , OpenWay GroupContinuous Integration, internal Python development, VM administration
Teaching
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2023, 2024, 2025 Spring -
2023, 2024 Fall -
2021, 2022 Spring
Volunteer
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Jun 2022 - May 2024 Remote
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Jun 2022 - Nov 2022 Remote
Publications
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Oct 2026 Lawyer: Modular Obligations-Based Liveness Reasoning in Higher-Order Impredicative Concurrent Separation Logic
Egor Namakonov, Justus Fasse, Bart Jacobs, Lars Birkedal, Amin Timany
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Feb 2026 Verifying wait-freedom of higher-order programs [preprint]
Egor Namakonov, Lars Birkedal, Amin Timany
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Oct 2021 Making weak memory models fair
Ori Lahav, Egor Namakonov, Jonas Oberhauser, Anton Podkopaev, Viktor Vafeiadis
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Dec 2019 Compilation of OCaml memory model into Power
Egor Namakonov, Anton Podkopaev
also see more details
Skills
| Programming languages | |
| OCaml | |
| Python | |
| Rust | |
| also: Haskell, C, Java, Kotlin, Elisp, Groovy... |
| Formal verification tools | |
| Rocq proof assistant | |
| Iris separation logic |
| Automation tools | |
| Vagrant | |
| Docker | |
| Travis CI | |
| Jenkins |
| Theory | |
| Formal logic | |
| Dependent types |
Languages
| Russian | |
| Native speaker |
| English | |
| Fluent |
| Danish | |
| Intermediate |
| German | |
| Beginner |
Professional interests
| Formal verification |
| Concurrency |
| Weak memory |
| Liveness |
Projects
- Mar 2019 - Aug 2022
Intermediate Memory Model
A declarative memory model bridging the gap between the models of languages and processors
- Sep 2022 - present